Accurate NBTI-induced Gate Delay Modeling Based on Intensive SPICE Simulations

One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It increases the switching threshold voltage of pMOS transistors and as a result slows down signal propagation along the paths between flip-flops, thus it may cause functional failures in the circuit. Therefore accurate prediction of circuit aging is essential to reliable design, especially for mission or safety critical applications. In this paper, a predictive model to compute NBTI-induced gate delay degradation proposed in [10] has been further developed. The model relies on intensive SPICE electrical simulations carried out for different basic logic gates. The model is more accurate and advanced since it analyzes the impact of pMOS transistors physical location on gate delay degradation and possible delay decrease introduced by many-input NOR gate 1→0 input transition. The obtained results demonstrate an accurate fitting between the developed model and SPICE simulations for separate gates as well as for NBTI-induced delay critical paths with several orders of magnitude gain in simulation speed. Keywords—Negative Bias Temperature Instability (NBTI), aging, gate delay, predictive model, SPICE